Design Verification Engineer

The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques; designing verification components such as bus functional models, monitors, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification.

According to JobzMall, the average salary range for a Design Verification Engineer in 1320 Ridder Park Dr, San Jose, CA 95131, USA is between $110,000 and $130,000 per year. This range may vary depending on certain factors such as experience, industry, and company size.

Broadcom Inc. is an American designer, developer, manufacturer and global supplier of a wide range of semiconductor and infrastructure software products, Broadcom's product portfolio serves the data center, networking, software, broadband, wireless, and storage and industrial markets.