An organised, detailed and goal-oriented demeanour. Experienced Associate Engineer in Formal Verification with 2 years of
expertise using Cadence’s Jasper Gold and System Verilog. Proficient in coding assertions, debugging designs, and expanding
coverage. Adept at cross-functional teamwork and providing technical support. Skillful in time management through effective
prioritisation and enabling efficient task execution.

Currently a Master's student at Pennsylvania State University.
Actively seeking summer'24 internship.

Pennsylvania State University

Partnered with Intel Corporation as a Formal Verification Engineer of DVP (DTF Visa Packetizer) IP.
Trusted with verifying Intellectual Property(s) by writing assertions, studying waveforms, timing diagrams, and functionalities, checking and reporting potential bugs in the designs.
Handled end-to-end client’s IP, right from setting up the environment, developing test plans to filing HSDs for bugs.
Performed sandbox integration of multiple IPs, set up tool-related flow like Magillem and Collage and run regression.

Ganesh Yogiraj Gotaphode

#1 Video-Talent Marketplace

Ready to discover your perfect career?